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ltc4257-1 1 42571fb the ltc ? 4257-1 provides complete signature and power interface functions for a device operating in an ieee 802.3af power over ethernet (poe) system. the ltc4257-1 simplifies powered device (pd) design by incorporating the 25k signature resistor, classification current source, input current limit, undervoltage lockout, thermal over- load protection, signature disable and power good signal- ling, all in a single 8-pin package. the ltc4257-1 includes a precision, dual level current limit circuit. this allows it to charge large load capacitors and interface with legacy power over ethernet systems while maintaining compat- ibility with the current ieee 802.3af specification. by incorporating a high voltage power mosfet onboard, the ltc4257-1 provides the system designer with reduced cost while also saving board space. the ltc4257-1 can interface directly with a variety of lin- ear technology dc/dc converter products to provide a cost effective power solution for ip phones, wireless access points and other pds. linear technology also provides network power controllers for power sourcing equipment (pse) applications. the ltc4257-1 is available in the 8-pin so and low profile (3mm 3mm) dfn packages. ip phone power management wireless access points telecom power control , ltc and lt are registered trademarks of linear technology corporation. complete power interface port for ieee 802 .3af powered devices (pds) onboard 100v, 400ma power mosfet precision dual level current limit onboard 25k signature resistor with disable programmable classification current (class 0-4) undervoltage lockout thermal overload protection power good signal available in 8-pin so and low profile (3mm 3mm) dfn packages ieee 802.3af pd power over ethernet interface controller with dual current limit gnd r class r class smaj58a 0.1 f sigdisa pwrgd ltc4257-1 v in shdn 100k 5 f min 3.3v to logic rtn switching power supply v in v out C48v from power sourcing equipment (pse) 42571 ta01 + C + df01sa ~ ~ + C powered device (pd) descriptio u features applicatio s u typical applicatio u all other trademarks are the property of their respective owners.
ltc4257-1 2 42571fb symbol parameter conditions min typ max units v in supply voltage voltage with respect to gnd pin (notes 4, 5, 6) maximum operating voltage C57 v signature range C 1.5 C 9.5 v classification range C 12.5 C 21 v uvlo turn-on voltage C 34.8 C36.0 C 37.2 v uvlo turn-off voltage C 29.3 C30.5 C 31.5 v i in_on ic supply current when on v in = C 48v, pins 5, 6, 7 floating 3ma i in_class ic supply current during classification v in = C 17.5v, pins 2, 7 floating, v out tied to gnd 0.35 0.50 0.65 ma (note 7) ? i class current accuracy during classification 10ma < i class < 40ma, C 12.5v v in C 21v, 3.5 % (notes 8, 9) r signature signature resistance C1.5v v in C9.5v, v out tied to gnd, 23.25 26.00 k ? ieee 802.3af 2-point measurement (notes 4, 5) r invalid invalid signature resistance C 1.5v v in C 9.5v, sigdisa and v out 9 11.8 k ? tied to gnd, ieee 802.3af 2-point measurement (notes 4, 5) (notes 1, 2) v in voltage ............................................. 0.3v to C 100v v out , sigdisa, pwrgd voltage ...................... v in + 100v to v in C 0.3v r class voltage ............................ v in + 7v to v in C 0.3v pwrgd current .................................................. 10ma r class current .................................................. 100ma the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) absolute axi u rati gs w ww u electrical characteristics consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grades are identified by a label on the shipping container. package/order i for atio uu w operating ambient temperature range ltc4257c-1 ............................................ 0 c to 70 c ltc4257i-1 ......................................... C40 c to 85 c storage temperature range s8 package ....................................... C 65 c to 150 c dd package ...................................... C 65 c to 125 c lead temperature (soldering, 10 sec).................. 300 c order part number 1 2 3 4 8 7 6 5 top view gnd sigdisa pwrgd v out nc r class nc v in s8 package 8-lead plastic so t jmax = 150 c, ja = 150 c/w top view dd package 8-lead (3mm 3mm) plastic dfn 5 6 7 8 4 3 2 1 nc r class nc v in gnd sigdisa pwrgd v out t jmax = 125 c, ja = 43 c/w exposed pad to be soldered to electrically isolated pcb heatsink s8 part marking 42571 4257i1 ltc4257cs8-1 ltc4257is8-1 order part number dd part marking* lbfz ltc4257cdd-1 ltc4257idd-1 order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/
ltc4257-1 3 42571fb v ih signature disable with respect to v in , high level input voltage high level invalidates signature (note 10) 357v v il signature disable with respect to v in , low level input voltage low level enables signature 0.45 v r input signature disable with respect to v in input resistance 100 k ? v pg_out power good output low voltage i = 1ma, v in = C 48v, pwrgd referenced to v in 0.5 v power good trip point v in = C48v, voltage between v in and v out (note 9) v pg_thres_fall v out falling 1.3 1.5 1.7 v v pg_thres_rise v out rising 2.7 3.0 3.3 v i pg_leak power good leakage v in = 0v, pwrgd fet off, v pwrgd = 57v 1 a r on on-resistance i = 350ma, v in = C 48v, measured from v in to v out 1.0 1.6 ? (note 9) 2.0 ? i out_leak v out leakage v in = 0v, power mosfet off, v out = 57v (note 11) 150 a i limit_high input current limit, high level v in = C 48v, v out = C43v (notes 12, 13) 0 c t a 70 c 350 375 400 ma C40 c t a 85 c 340 375 400 ma i limit_low input current limit, low level v in = C 48v, v out = C43v (notes 12, 13) 100 140 180 ma t shutdown thermal shutdown trip temperature (notes 12, 14) 140 c symbol parameter conditions min typ max units the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltages are with respect to gnd pin unless otherwise noted. note 3: the ltc4257-1 operates with a negative supply voltage in the range of C1.5v to C57v. to avoid confusion, voltages in this data sheet are always referred to in terms of absolute magnitude. terms such as maximum negative voltage refer to the largest negative voltage and a rising negative voltage refers to a voltage that is becoming more negative. note 4: the ltc4257-1 is designed to work with two polarity protection diode drops between the pse and pd. parameter ranges specified in the electrical characteristics are with respect to ltc4257-1 pins and are designed to meet ieee 802.3af specifications when these diode drops are included. see applications information. note 5: signature resistance is measured via the 2-point ? v/ ? i method as defined by ieee 802.3af. the ltc4257-1 signature resistance is offset from 25k to account for diode resistance. with two series diodes, the total pd resistance will be between 23.75k ? and 26.25k ? and meet ieee 802.3af specifications. the minimum probe voltages measured at the ltc4257-1 pins are C1.5v and C2.5v. the maximum probe voltages are C8.5v and C9.5v. note 6: the ltc4257-1 includes hysteresis in the uvlo voltages to preclude any start-up oscillation. per ieee 802.3af requirements, the ltc4257-1 will power up from a voltage source with 20 ? series resistance on the first trial. note 7: i in_class does not include classification current programmed at pin 2. total supply current in classification mode will be i in_class + i class (see note 8). note 8: i class is the measured current flowing through r class . ? i class accuracy is with respect to the ideal current defined as i class = 1.237/r class . the current accuracy specification does not include variations in r class resistance. the total classification current for a pd also includes the ic quiescent current (i in_class ). see applications information. note 9: for the dd package, this parameter is assured by design and wafer level testing. note 10: to disable the 25k signature, tie sigdisa to gnd ( 0.1v) or hold sigdisa high with respect to v in . see applications information. note 11: i out_leak includes current drawn at the v out pin by the power good status circuit. this current is compensated for in the 25k ? signature resistance and does not affect pd operation. note 12: the ltc4257-1 includes thermal protection. in the event of an overtemperature condition, the ltc4257-1 will turn off the power mosfet until the part cools below the overtemperature limit. the ltc4257-1 is also protected against thermal damage from incorrect classification probing by the pse. if the ltc4257-1 exceeds the overtemperature trip point, the classification load current is disabled. note 13: the ltc4257-1 includes dual level input current limit. at turn-on, before c1 is charged, the ltc4257-1 current level is set to the low level. after c1 is charged and the v out C v in voltage difference is below the power good threshold, the ltc4257-1 switches to high level current limit. the ltc4257-1 stays in high level current limit until the input voltage drops below the uvlo turn-off threshold. note 14: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125 c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. electrical characteristics
ltc4257-1 4 42571fb signature resistance vs input voltage normalized uvlo threshold vs temperature typical perfor a ce characteristics uw v out leakage current current limit vs input voltage input current vs input voltage input current vs input voltage 25k detection range input current vs input voltage input voltage (v) 0 0 input current (ma) 0.1 0.2 0.3 0.4 0.5 C2 C4 C6 C8 4357 g01 C10 t a = 25 c input voltage (v) 0 0 input current (ma) 10 20 30 40 50 C10 C20 C30 C40 42571 g02 C50 C60 class 4 class 3 class 2 class 1 class 0 t a = 25 c input voltage (v) C12 9.0 input current (ma) 9.5 10.5 11.0 11.5 C14 C16 42571 g03 10.0 C18 C20 C22 12.0 85 c C40 c class 1 operation input current vs input voltage input voltage (v) 0 input current (ma) 1 2 3 C45 C55 42571 g04 C60 C40 C50 excludes any load current t a = 25 c input voltage (v) C1 22 v1: v2: signature resistance (k ? ) 23 25 26 27 C3 C5 42571 g05 24 C7 C9 C6 C10 C2 C4 C8 28 resistance = diodes: s1b t a = 25 c = ? v ? i v2 C v1 i 2 C i 1 ieee upper limit ieee lower limit ltc4257-1 + 2 diodes ltc4257-1 only temperature ( c) C40 C2 normalized uvlo threshold (%) C1 0 1 2 C20 0 20 40 42571 g06 60 80 applicable to turn-on and turn-0ff thresholds power good output low voltage vs current current (ma) 0 v pg_out (v) 2 3 8 42571 g07 1 0 2 4 6 10 4 t a = 25 c v out pin voltage (v) 0 0 v out current ( a) 30 60 120 90 20 40 42571 g08 60 v in = 0v t a = 25 c input voltage (v) C40 current limit (ma) 200 C60 42571 g09 100 C45 C50 C55 400 300 85 c 85 c C40 c C40 c high current mode low current mode
ltc4257-1 5 42571fb nc (pin 1): no internal connection. r class (pin 2): class select input. used to set the current value the ltc4257-1 maintains during classification. con- nect a resistor between r class and v in (see table 2). nc (pin 3): no internal connection. v in (pin 4): power input. tie to system C 48v through the input diode bridge. v out (pin 5): power output. supplies C 48v to the pd load through an internal power mosfet that limits input cur- rent. v out is high impedance until the input voltage rises above the turn-on uvlo threshold. the output is then current limited. see applications information. pwrgd (pin 6): power good output, open-drain. signals to the pd load that the ltc4257-1 mosfet is on and that the pds dc/dc converter can start operation. low imped- ance indicates power is good. pwrgd is high impedance during detection, classification and in the event of a thermal overload. pwrgd is referenced to v in . sigdisa (pin 7): signature disable input. allows the pd to command the ltc4257-1 to present an invalid signa- ture resistance and to remain inactive. connecting sigdisa to gnd lowers the signature resistance to an invalid value and disables all functions of the ltc4257-1. if left floating, sigdisa is internally pulled to v in . if unused, tie sigdisa to v in . gnd (pin 8): ground. tied to system ground and power return through the input diode bridge. uu u pi fu ctio s block diagra w 42571 bd v in bold line indicates high current path v out C + 8 5 4 nc 3 r class 2 nc pwrgd sigdisa gnd 1 7 6 control circuits input current limit power good classification current load 1.237v en 375ma 140ma signature disable 9k 16k 0.3 ? C + en 25k signature resistor
ltc4257-1 6 42571fb the ltc4257-1 is intended for use as the front end of a powered device (pd) adhering to the ieee 802.3af standard. the ltc4257-1 includes a trimmed 25k signature resistor, classification current source, and an input current limit cir- cuit. with these functions integrated into the ltc4257-1, the signature and power interface for a pd that meets all the requirements of the ieee 802.3af specification can be built with a minimum of external components. the ltc4257-1 has been specifically designed to interface with legacy poe pses which do not meet the inrush current requirement of the ieee 802.3af specification. by setting the initial inrush current limit to a low level, a pd using the ltc4257-1 minimizes the current drawn from the pse during start-up. after powering up, the ltc4257-1 switches to the high level current limit, thereby allowing the pd to consume up to 12.95 watts if an 802.3af pse is present. this low level current limit also allows the ltc4257-1 to charge arbitrarily large load capacitors without exceeding the inrush limits of the ieee 802.3af specification. this dual level current limit provides the system designer with flexibility to design pds which are compatible with legacy pses while also being able to take advantage of the higher power allocation available in an ieee 802.3af system. using an ltc4257-1 for the power and signature inter- face functions of a pd provides several advantages. the ltc4257-1 current limit circuit includes an onboard, 100v, 400ma power mosfet with low leakage. this onboard low leakage mosfet avoids the possibility of corrupting the 25k signature resistor while also saving board space and cost. in addition, the inrush current limit requirement of the ieee 802.3af standard causes large transient power dissipation in the pd. the ltc4257-1 is designed to allow multiple turn-on sequences without overheating the miniature 8-lead package. in the event of excessive power cycling, the ltc4257-1 provides ther- mal overload protection to keep the onboard power mosfet within its safe operating area. operation the ltc4257-1 has several modes of operation depend- ing on the applied input voltage as shown in figure 1 and detection v1 classification uvlo turn-on uvlo off power bad uvlo off uvlo on uvlo turn-off = r load c1 pwrgd tracks v in detection v2 10 time 20 30 v in (v) 40 50 10 time 20 30 v out (v) 40 50 10 time 20 30 pwrgd (v) 40 50 i class pd current i limit dv dt i limit c1 = power bad power good detection i 1 classification i class detection i 2 load, i load current limit, i limit 42571 f01 i class dependent on r class selection i limit = 140ma (nominal) i 1 = v1 C 2 diode drops 25k ? i load = v in r load i 2 = v2 C 2 diode drops 25k ? gnd 2 pse i in ltc4257-1 8 6 5 r9 r load r class v out c1 gnd 4 r class pwrgd v out v in v in figure 1. output voltage, pwrgd and pd current as a function of input voltage applicatio s i for atio wu uu
ltc4257-1 7 42571fb summarized in table 1. these various modes satisfy the requirements defined in the ieee 802.3af specification. the input voltage is applied to the v in pin and is with reference to the gnd pin. this input voltage is always negative. to avoid confusion, voltages in this data sheet are always referred to in terms of absolute magnitude. terms such as maximum negative voltage refer to the largest negative voltage and a rising negative voltage refers to a voltage that is becoming more negative. refer- ences to electrical parameters in this applications section use the nominal value. refer to the electrical characteris- tics section for the range of values a particular parameter will have. table 1. ltc4257-1 operational mode as a function of input voltage input voltage (v in with respect to gnd) ltc4257-1 mode of operation 0v to C 1.4v inactive C 1.5v to C 10v 25k signature resistor detection C 11v to C 12.4v classification load current ramps up from 0% to 100% C 12.5v to uvlo* classification load current active uvlo* to C57v power applied to pd load *uvlo includes hysteresis. rising input threshold ? C 36.0v falling input threshold ? C 30.5v figure 2. pd front end using diode bridges on main and spare inputs series diodes the ieee 802.3af defined operating modes for a pd reference the input voltage at the rj45 connector on the pd. however, pd circuitry must include diode bridges between the rj45 connector and the ltc4257-1 (figure 2). the ltc4257-1 takes this into account by compensat- ing for these diode drops in the threshold points for each range of operation. since the voltage ranges specified in the ltc4257-1 electrical specifications are with respect to the ic pins, for both the signature and classification ranges, the ltc4257-1 lower end extends two diode drops below the ieee 802.3af specification. a similar adjustment is made for the uvlo voltages. detection during detection, the pse will apply a voltage in the range of C2.8v to C10v on the cable and look for a 25k signature resistor. this identifies the device at the end of the cable as a pd. with the terminal voltage in this range, the ltc4257-1 connects an internal 25k resistor between gnd and the v in pins. this precision, temperature compensated resistor presents the proper characteristics to alert the power sourcing equipment (pse) at the other end of the cable that a pd is present and desires power to be applied. applicatio s i for atio wu uu rx C 6 rx + 3 tx C 2 tx + rj45 t1 powered device (pd) interface as defined by ieee 802.3af 42571 f02 1 7 8 5 4 spare C spare + to phy br2 br1 gnd 8 4 d3 ltc4257-1 v in
ltc4257-1 8 42571fb classification once the pse has detected a pd, the pse may optionally classify the pd. classification provides a method for more efficient allocation of power by allowing the pse to identify lower-power pds and allocate less power for these de- vices. the ieee 802.3af specification defines five classes (table 2) with varying power levels. the designer selects the appropriate classification based on the power con- sumption of the pd. for each class, there is an associated load current that the pd asserts onto the line during classification probing. the pse measures the pd load current to determine the proper classification and pd power requirements. table 2. summary of ieee 802.3af power classifications and ltc4257-1 r class resistor selection maximum nominal ltc4257-1 power levels classification r class at input of pd load current resistor class usage (w) (ma) ( ? , 1%) 0 default 0.44 to 12.95 < 5 open 1 optional 0.44 to 3.84 10.5 124 2 optional 3.84 to 6.49 18.5 68.1 3 optional 6.49 to 12.95 28 45.3 4 reserved reserved* 40 30.9 *class 4 is currently reserved and should not be used. early revisions of the ieee 802.3af draft specification defined two methods that a pse could use in order to perform pd classification. these methods are known as measured current and measured voltage. the ieee has since removed the measured voltage method from the the power applied to a pd is allowed to use either of two polarities and the pd must be able to accept this power so it is common to install a diode bridge on the input. the ltc4257-1 is designed to compensate for the voltage and resistance effects of these two series diodes. the signa- ture range extends below the ieee range to accommodate the voltage drop of the diodes. the ieee specification requires the pse to use a ? v/ ? i measurement technique to keep the dc offset of these diodes from affecting the signature resistance measurement. however, the diode resistance appears in series with the signature resistor and must be included in the overall signature resistance of the pd. the ltc4257-1 compensates for the two series diodes in the signature path by offsetting the resistance so that a pd built using the ltc4257-1 will meet the ieee specification. in some applications it is necessary to control whether or not the pd is detected. in this case, the 25k signature can be enabled and disabled with the use of the sigdisa pin (figure 3). disabling the signature via the sigdisa pin will change the signature resistor to 9k which is an invalid sig- nature per the ieee 802.3af specification. this invalid signature is present for pd input voltages from C2.8v to C10v. if the input rises above C10v, the signature resis- tor reverts to 25k to minimize power dissipation in the ltc4257-1. to disable the signature, tie sigdisa to gnd. alternately, the sigdisa pin can be driven high with re- spect to v in . when sigdisa is high, all functions of the ltc4257-1 are disabled. figure 3. 25k signature resistor with disable applicatio s i for atio wu uu gnd v in 8 7 4 ltc4257-1 42571 f03 25k signature resistor signature disable sigdisa 9k 16k to pse
ltc4257-1 9 42571fb specification. the ltc4257-1 is compatible with the ieee 802.3af standard and also works with the obsolete mea- sured voltage method. in the measured current method (figure 4), the pse presents a fixed voltage between C15.5v and C20.5v to the pd. with the input voltage in this range, the ltc4257-1 asserts a load current from the gnd pin through the r class resistor. the magnitude of the load current is set with the selection of the r class resistor. the resistor value associated with each class is shown in table 2. in the measured voltage method (figure 5), the pse drives a current into the pd and monitors the voltage across the pd terminals. the pse current steps between classifica- tion load current values in order to classify the pd under test. for pse probe currents below the pd load current, the ltc4257-1 will keep the pd terminal voltage below the classification voltage range. for pse probe currents above the pd load current, the ltc4257-1 will force the pd terminal voltage above the classification voltage range. during classification, a moderate amount of power is dissipated in the ltc4257-1. the ieee 802.3af specifica- tion limits the classification time to 75ms. the ltc4257-1 is designed to handle the power dissipation for this time period. if the pse probing exceeds 75ms, the ltc4257-1 may overheat. in this situation, the thermal protection circuit will engage and disable the classification current source in order to protect the part. the ltc4257-1 stays in classification mode until the input voltage rises above the uvlo turn-on voltage. applicatio s i for atio wu uu figure 5. ieee 802.af measured-voltage method of classification probing gnd r class v in 8 2 4 ltc4257-1 constant load current internal to ltc4257-1 42571 f05 r class current path v pd pse pse voltage monitor pse probing current source if pse probing current < ltc4257-1 load current, pd terminal voltage is < 15v if pse probing current > ltc4257-1 load current, pd terminal voltage is > 20v gnd r class v in 8 2 4 ltc4257-1 constant load current internal to ltc4257-1 42571 f04 r class current path v pd pse pse current monitor pse probing voltage source C15.5v to C20.5v figure 4. ieee 802.3af measured-current method of classification probing
ltc4257-1 10 42571fb undervoltage lockout the ieee specification dictates a maximum turn-on volt- age of 42v and a minimum turn-off voltage of 30v for the pd. in addition, the pd must maintain large on-off hyster- esis to prevent resistive losses in the wiring between the pse and the pd from causing start-up oscillation. the ltc4257-1 incorporates an undervoltage lockout (uvlo) circuit that monitors line voltage to determine when to apply power to the pd load (figure 6). before power is applied to the load, the v out pin is high impedance and sitting at ground potential since there is no charge on capacitor c1. when the input voltage rises above the uvlo turn-on threshold, the ltc4257-1 removes the classifica- tion load current and turns on the internal power mosfet. c1 charges up under ltc4257-1 current limit control and the v out pin transitions from 0v to v in . this sequence is shown in figure 1. the ltc4257-1 includes a hysteretic uvlo circuit that keeps power applied to the load until the input voltage falls below the uvlo turn-off threshold. once the input voltage drops below C30v, the internal power mosfet is turned off and the classification load current is re-enabled. c1 will discharge through the pd circuitry and the v out pin will go to a high impedance state. input current limit ieee 802.3af specifies a maximum inrush current and also specifies a minimum load capacitor between the gnd and v out pins. to control turn-on surge current in the system, the ltc4257-1 integrates a dual level current limit circuit with an onboard power mosfet and sense resistor to provide a complete inrush control circuit without additional external components. at turn on, the ltc4257-1 will limit input current to the low level, allowing the load capacitor to ramp up to the line voltage in a controlled manner. the ltc4257-1 has been specifically designed to interface with legacy pses which do not meet the inrush current requirement of the ieee 802.3af specification. this is applicatio s i for atio wu uu gnd c1 5 f min v in 8 4 v out 5 ltc4257-1 42571 f06 to pse undervoltage lockout circuit pd load current-limited turn on + input ltc4257-1 voltage power mosfet 0v to uvlo* off >uvlo* on *uvlo includes hysteresis rising input threshold ? C36v falling input threshold ? C30.5v figure 6. ltc4257-1 undervoltage lockout
ltc4257-1 11 42571fb accomplished by a dual level current limit. at turn on before c1 is charged, the ltc4257-1 current limit is set to the low level. after c1 is charged up and the v out C v in voltage difference is below the power good threshold, the ltc4257-1 switches to the high level current limit. the dual level current limit allows legacy pses with limited current sourcing capability to power up the pd while also allowing the pd to draw full power from an ieee 802.3af pse. the dual level current limit also allows use of arbitrarily large load capacitors. the ieee 802.3af specification man- dates that at turn on the pd not exceed the inrush current limit for more than 50ms. the ltc4257-1 is not restricted by the 50ms time limit because the load capacitor is charged with a current below the ieee inrush current limit specification. therefore, it is possible to use larger load capacitors with the ltc4257-1. as the ltc4257-1 switches from the low to the high level current limit, a momenatry increase in current can be observed. this current spike is a result of the ltc4257-1 charging the last 1.5v at the high level current limit. when charging a 10 f capacitor, the current spike is typically 100 s wide and 125% of the nominal low level current limit. the ltc4257-1 stays in the high level current limit mode until the input voltage drops below the uvlo turn-off threshold. this dual level current limit provides the sys- tem designer with the flexibility to design pds which are compatible with legacy pses while also being able to take advantage of the higher power allocation available in an ieee 802.3af system. during the current limited turn on, a large amount of power is dissipated in the power mosfet. the ltc4257-1 is designed to accept this thermal load and is thermally protected to avoid damage to the onboard power mosfet. note that in order to adhere to the ieee 802.3af standard, it is necessary for the pd designer to ensure the pd steady- state power consumption falls within the limits shown in table 2. power good the ltc4257-1 includes a power good circuit (figure 7) that is used to indicate to the pd circuitry that load capacitor c1 is fully charged and that the pd can start dc/dc converter operation. the power good circuit moni- tors the voltage across the internal power mosfet and pwrgd is asserted when the voltage drops below 1.5v. the power good circuit includes a large amount of hyster- esis to allow the ltc4257-1 to operate near the current limit point without inadvertently disabling pwrgd. the mosfet voltage must increase to 3v before pwrgd is disabled. applicatio s i for atio wu uu figure 7. ltc4257-1 power good pwrgd c1 5 f min v in 6 4 v out 1.125v 300k 300k r9 100k 5 ltc4257-1 thermal shutdown uvlo 42571 f07 to pse pd load shdn + C + + C
ltc4257-1 12 42571fb if a sudden increase in voltage appears on the input line, this voltage step will be transferred through capacitor c1 and appear across the power mosfet. the response of the ltc4257-1 will depend on the magnitude of the voltage step, the rise time of the step, the value of capacitor c1 and the dc load. for fast rising inputs, the ltc4257-1 will attempt to quickly charge capacitor c1 using an internal secondary current limit circuit. in this scenario, the pse current limit should provide the overall limit for the circuit. for slower rising inputs, the 375ma current limit in the ltc4257-1 will set the charge rate of capacitor c1. in either case, the pwrgd signal may go inactive briefly while the capacitor is charged up to the new line voltage. in the design of a pd, it is necessary to determine if a step in the input voltage will cause the pwrgd signal to go inactive and how to respond to this event. in some designs, the charge on c1 is sufficient to power the pd through this event. in this case, it may be desirable to filter the pwrgd signal so that intermittent power bad condi- tions are ignored. figure 10 demonstrates methods to insert a lowpass filter on the power good interface. for pd designs that use a large load capacitor and also consume a lot of power, it is important to delay activation of the pd circuitry with the pwrgd signal. if the pd cir- cuitry is not disabled during the current-limited turn-on se- quence, the pd circuitry will rob current intended for charg- ing up the load capacitor and create a slow rising input, possibly causing the ltc4257-1 to go into thermal shut- down. the pwrgd pin connects to an internal open-drain, 100v transistor capable of sinking 1ma. low impedance indi- cates power is good. pwrgd is high impedance during signature and classification probing and in the event of a thermal overload. during turn-off, pwrgd is deactivated when the input voltage drops below 30v. in addition, pwrgd may go active briefly at turn-on for fast rising input waveforms. pwrgd is referenced to the v in pin and when active will be near the v in potential. the pd dc/dc converter will typically be referenced to v out and care must be taken to ensure that the difference in potential of the pwrgd signal does not cause any detrimental effects. use of diode clamp d6, as shown in figure 10, will alleviate any problems. thermal protection the ltc4257-1 includes thermal overload protection in order to provide full device functionality in a miniature package while maintaining safe operating temperatures. several factors create the possibility for tremendous power dissi pation within the ltc4257-1. at turn on, before the load capacitor has charged up, the instanta- neous power dissipated by the ltc4257-1 can be 10w. as the load capacitor charges up, the power dissipation in the ltc4257-1 will decrease until it reaches a steady-state value dependent on the dc load current. the size of the load capacitor determines how fast the power dissipation in the ltc4257-1 will subside. at room temperature, the ltc4257-1 can handle load capacitors as large as 800 f without going into thermal shutdown. with a large load capacitor like this, the ltc4257-1 die temperature will increase by about 50 c during a single turn-on sequence. if for some reason power were removed from the part and then quickly reapplied so that the ltc4257-1 has to charge up the load capacitor again, the temperature rise would be excessive if safety precautions were not implemented. the ltc4257-1 protects itself from thermal damage by monitoring the die temperature. if the die temperature exceeds the overtemperature trip point, the current is reduced to zero and very little power is dissipated in the part until it cools below the overtemperature set point. once the ltc4257-1 has charged up the load capacitor and the pd is powered and running, there will be some residual heating due to the dc load current of the pd flowing through the internal mosfet. in some applica- tions, the ltc4257-1 power dissipation may be signifi- cant and if dissipated in the s8 package, excessive pack- age heating could occur. this problem can be solved with the use of the dd package which has superior thermal performance. the dd package includes an exposed pad which should be soldered to an isolated heatsink on the printed circuit board. during classification, excessive heating of the ltc4257-1 can occur if the pse violates the 75ms probing time limit. to protect the ltc4257-1, thermal protection circuitry will disable classification current if the die temperature exceeds applicatio s i for atio wu uu
ltc4257-1 13 42571fb applicatio s i for atio wu uu the overtemperature trip point. when the die cools down below the trip point, classification current is enabled again. if the pd is designed to operate at a high ambient tempera- ture and with the maximum allowable supply (57v), there will be a limit to the size load capacitor that can be charged up before the ltc4257-1 reaches the overtemperature trip point. hitting the overtemperature trip point intermittently does not harm the ltc4257-1, but it will delay completion of capacitor charging. capacitors up to 200 f can be charged without a problem. external interface and component selection transformer nodes on an ethernet network commonly interface to the outside world via an isolation transformer (figure 8). for powered devices, the isolation transformer must include a center tap on the media (cable) side. proper termination is required around the transformer to provide correct impedance matching and to avoid radiated and conducted emissions. transformer vendors such as pulse, bel fuse, tyco and others (table 3) can provide assistance with selection of an appropriate isolation transformer and proper termination methods. these vendors have trans- formers specifically designed for use in pd applications. table 3. power over ethernet transformer vendors vendor contact information pulse engineering 12220 world trade drive san diego, ca 92128 tel: 858-674-8100 fax: 858-674-8262 http://www.pulseeng.com/ bel fuse inc. 206 van vorst street jersey city, nj 07302 tel: 201-432-0463 fax: 201-432-9542 http://www.belfuse.com/ tyco electronics 308 constitution drive menlo park, ca 94025-1164 tel: 800-227-7040 fax: 650-361-2508 http://www.circuitprotection.com/ diode bridges ieee 802.3af allows power wiring in either of two configu- rations on the tx/rx wires, plus power can be applied to the pd via the spare wire pair in the rj45 connector. the pd is required to accept power in either polarity on both the main and spare inputs; therefore, it is common to install diode bridges on both inputs in order to accommo- date the different wiring configurations. figure 8 demon- strates an implementation of these diode bridges. the specification also mandates that the leakage back through the unused bridge be less than 28 a when the pd is powered with 57v. figure 8. pd front end with isolation transformer, diode bridges and capacitor 16 14 15 1 3 2 rx C 6 rx + 3 tx C 2 tx + rj45 t1 pulse h2019 42571 f08 1 7 8 5 4 11 9 10 6 8 7 d3 smaj58a tvs br1 df01sa br2 df01sa to phy gnd 8 5 4 ltc4257-1 c1 v in v out v out spare C spare + c14 0.1 f 100v
ltc4257-1 14 42571fb applicatio s i for atio wu uu the ieee standard includes an ac impedance requirement in order to implement the ac disconnect function. capaci- tor c14 in figure 8 is used to meet this ac impedance requirement. a 0.1 f capacitor is recommended for this application. the ltc4257-1 has several different modes of operation based on the voltage present between the v in and gnd pins. the forward voltage drop of the input diodes in a pd design subtracts from the input voltage and will affect the transi- tion point between modes. when using the ltc4257-1, it is necessary to pay close attention to this forward voltage drop. selection of oversized diodes will help keep the pd thresholds from exceeding ieee specifications. the input diode bridge of a pd can consume over 4% of the available power in some applications. it may be desirable to use schottky diodes in order to reduce this power loss. however, if the standard diode bridge is replaced with a schottky bridge, the transition points between modes will be affected. the application circuit (figure 11) shows a tech- nique for using schottky diodes while maintaining proper threshold points to meet ieee 802.3af compliance. auxiliary power source in some applications, it may be desirable to power the pd from an auxiliary power source such as a wall transformer. the auxiliary power can be injected into the pd at several locations and various trade-offs exist. power can be injected at the 3.3v or 5v output of the isolated power supply with the use of a diode oring circuit. this method accesses the internal circuits of the pd after the isolation barrier and therefore meets the 802.3af isolation safety requirements for the wall transformer jack on the pd. power can also be injected into the pd interface portion of the lt4257-1. in this case, it is necessary to ensure the user cannot access the terminals of the wall transformer jack on the pd since this would compromise the 802.3af isolation safety requirements. figure 9 demonstrates three methods of diode oring external power into a pd. option 1 inserts power before the ltc4257-1 while options 2 and 3 apply power after the ltc4257-1. if power is inserted before the ltc4257-1 (option 1), it is necessary for the wall transformer to exceed the ltc4257-1 uvlo turn-on requirement and limit the maximum voltage to 57v. this option provides input current limit for the transformer, provides a valid power good signal and simplifies power priority issues. as long as the wall transformer applies power to the pd before the pse, it will take priority and the pse will not power up the pd because the wall power will corrupt the 25k signature. if the pse is already powering the pd, the wall transformer power will be in parallel with the pse. in this case, priority will be given to the higher supply voltage. if the wall transformer voltage is higher, the pse should remove line voltage since no current will be drawn from the pse. on the other hand, if the wall transformer voltage is lower, the pse will continue to supply power to the pd and the wall trans- former power will not be used. proper operation should occur in either scenario. if auxiliary power is applied after the ltc4257-1 (option 2), a different set of tradeoffs arise. in this configuration, the wall transformer does not need to exceed the ltc4257-1 turn-on uvlo requirement; however, it is necessary to include diode d9 to prevent the transformer from applying power to the ltc4257-1. the transformer voltage require- ments will be governed by the needs of the pd switcher and may exceed 57v. however, power priority issues require more intervention. if the wall transformer voltage is below the pse voltage, then priority will be given to the pse power. the pd will draw power from the pse while the transformer will sit unused. this configuration is not a problem in a poe system. on the other hand, if the wall transformer voltage is higher than the pse voltage, the pd will draw power from the transformer. in this situation, it is necessary to address the issue of power cycling that may occur if a pse is present. the pse will detect the pd and apply power. if the pd is being powered by the wall transformer, then the pd will not meet the minimum load requirement and the pse will subse- quently remove power. the pse will again detect the pd and power cycling will start. with a transformer voltage above the pse voltage, it is necessary to either disable the signa- ture, as shown in option 2, or install a minimum load on the output of the ltc4257-1 to prevent power cycling. the third option also applies power after the ltc4257-1, while omitting diode d9. with the diode omitted, the transformer voltage is applied to the ltc4257-1 in addi- tion to the load. for this reason, it is necessary to ensure
ltc4257-1 15 42571fb applicatio s i for atio wu uu figure 9. auxiliary power source for pd rx C 6 rx + 3 tx C 2 tx + rj45 t1 1 7 8 5 4 spare C + C spare + isolated wall transformer to phy gnd 8 45 option 1: auxilary power inserted before ltc4257-1 option 2: auxilary power inserted after ltc4257-1 with signature disabled v in v out 38v to 57v d8 s1b d3 smaj58a tvs c1 pd load c14 0.1 f 100v rx C 6 rx + 3 tx C 2 tx + rj45 t1 1 7 8 5 4 spare C + C spare + isolated wall transformer to phy gnd sigdisa ltc4257-1 ltc4257-1 br2 df01sa ~ ~ + C br1 df01sa ~ ~ + C br1 df01sa ~ ~ + C 8 7 45 v in v out 42571 f09 d10 s1b d3 smaj58a tvs c1 100k pd load d9 s1b option 3: auxilary power applied to ltc4257-1 and pd load rx C 6 rx + 3 tx C 2 tx + rj45 t1 1 7 8 5 4 spare C + C spare + isolated wall transformer to phy 38v to 57v gnd ltc4257-1 8 45 v in v out d10 s1b d3 smaj58a tvs c1 pd load c14 0.1 f 100v c14 0.1 f 100v br2 df01sa ~ ~ + C br1 df01sa ~ ~ + C br2 df01sa ~ ~ + C 100k bss63
ltc4257-1 16 42571fb applicatio s i for atio wu uu that the transformer maintain the voltage between 38v and 57v to keep the ltc4257-1 in its normal operating range. the third option has the advantage of automatically dis- abling the 25k signature when the external voltage ex- ceeds the pse voltage. classification resistor selection (r class ) the ieee specification allows classifying pds into four distinct classes with class 4 being reserved for future use (table 2). an external resistor connected from r class to v in (figure 4) sets the value of the load current. the designer should determine which power category the pd falls into and then select the appropriate value of r class from table 2. if a unique load current is required, the value of r class can be calculated as: r class = 1.237v/(i desired C i in_class ) where i in_class is the ltc4257-1 ic supply current during classification and is given in the electrical speci- fications. the r class resistor must be 1% or better to avoid degrading the overall accuracy of the classification circuit. resistor power dissipation will be 50mw maxi- figure 10. power good interface examples mum and is transient so heating is typically not a con- cern. in order to maintain loop stability, the layout should minimize capacitance at the r class node. the classifica- tion circuit can be disabled by floating the r class pin. the r class pin should not be shorted to v in as this would force the ltc4257-1 classification circuit to attempt to source very large currents. in this case, the ltc4257-1 will quickly go into thermal shutdown. power good interface the pwrgd signal is controlled by a high voltage, open- drain transistor. examples of active-high and active-low interface circuits for controlling the pd load are shown in figure 10. in some applications it is desirable to ignore intermittent power bad conditions. this can be accomplished by including capacitor c15 in figure 10 to form a lowpass filter. with the components shown, power bad conditions less than about 200 s will be ignored. conversely, in other applications it may be desirable to delay assertion of pwrgd to the pd load. the pwrgd signal can be delayed with the addition of capacitor c17 in figure 10. gnd c1 5 f 100v v in 8 4 C48v v out 5 *c15 optional to filter pwrgd. see applications information ltc4257-1 pd load shdn pwrgd 6 d6 5.1v mmbz5231b c15* 0.047 f 10v r9 100k r9 100k r18 10k r18 10k + gnd c1 5 f 100v q1 fmmt2222 d6 mmbd4148 v in 8 4 C48v v out 5 ltc4257-1 42571 f10 pd load run c17* pwrgd 6 internal pullup + active-low enable, 5.1v swing active-high enable for run pin with internal pullup to pse to pse c15* 0.047 f 10v *c15 and c17 optional to filter pwrgd. see applications information
ltc4257-1 17 42571fb applicatio s i for atio wu uu signature disable interface to disable the 25k signature, connect the sigdisa pin to the gnd pin. alternately, sigdisa can be driven high with respect to v in . an example of a signature disable interface circuit is shown in figure 9, option 2. note that the sigdisa input resistance is relatively large and the threshold voltage is fairly low. because of high voltages present on the printed circuit board, leakage currents from the gnd pin could inadvertently pull sigdisa high. to insure trouble-free operation, use high-voltage layout techniques in the vicinity of sigdisa. if unused, connect sigdisa to v in . load capacitor the ieee 802.3af specification requires that the pd main- tain a minimum load capacitance of 5 f. it is permissible to have a much larger load capacitor and the ltc4257-1 can charge very large load capacitors before thermal issues become a problem. however, the load capacitor must not be too large or the pd design may violate ieee 802.3af requirements. if the load capacitor is too large there can be a problem with inadvertent power shutdown by the pse. consider the fol- lowing scenario. if the pse is running at C 57v (maximum allowed) and the pd has been detected and powered up, the load capacitor will be charged to nearly C 57v. if for some reason the pse voltage suddenly is reduced to C 44v (minimum allowed), the input bridge will reverse bias and pd power will be supplied solely by the load capacitor. depending on the size of the load capacitor and the dc load of the pd, the pd will not draw any power from the pse for a period of time. if this period of time exceeds the ieee 802.3af 300ms disconnect delay, the pse may remove power from the pd. for this reason, it is necessary to evaluate the load capacitance and load current to ensure that inadvertent shutdown cannot occur. very small output capacitors ( 10 f) will charge very quickly in current limit. the rapidly changing voltage at the output may reduce the current limit temporarily, causing the capacitor to charge at a somewhat reduced rate. conversely, charging very large capacitors may cause the current limit to increase slightly. in either case, once the output voltage reaches its final value, the input current limit will be restored to its nominal value. maintain power signature in an ieee 802.3af system, the pse uses the maintain power signature (mps) to determine if a pd continues to require power. the mps requires the pd to periodically draw at least 10ma and also have an ac impedance less than 26.25k ? in parallel with 0.05 f. the pd application circuits shown in this data sheet meet the requirements necessary to maintain power. if either the dc current is less than 10ma or the ac impedance is above 26.25k ? , the pse might disconnect power. the dc current must be less than 5ma and the ac impedance must be above 2m ? to guarantee power will be removed. layout the ltc4257-1 is relativity immune to layout problems. excessive parasitic capacitance on the r class pin should be avoided. if using the dd package, include an electrically isolated heat sink to which the exposed pad on the bottom of the package can be soldered. for optimum thermal performance, make the heatsink as large as possible. voltages in a pd can be as large as C 57v, so high voltage layout techniques should be employed. the load capacitor connected between pins 5 and 8 of the ltc4257-1 can store significant energy when fully charged. the design of a pd must ensure that this energy is not inadvertently dissipated in the ltc4257-1. the polarity- protection diode(s) prevent an accidental short on the cable from causing damage. however, if the v in pin is shorted to the gnd pin inside the pd while the load capacitor is charged, current will flow through the para- sitic body diode of the internal mosfet and may cause permanent damage to the ltc4257-1. electro static discharge and surge suppression the ltc4257-1 is specified to operate with an absolute maximum voltage of C 100v and is designed to tolerate brief overvoltage events. however, the pins that interface to the outside world (primarily v in and gnd) can routinely see peak voltages in excess of 10kv. to protect the ltc4257-1, it is highly recommended that a transient voltage suppressor be installed between the bridge and the ltc4257-1 (d3 in figure 2).
ltc4257-1 18 42571fb applicatio s i for atio wu uu ? 1 ? ? 5 4 ? 1 3 2 rx C spare C 6 rx + 3 tx C 2 tx + j2 in from pse t1 rj45 1 7 8 5 4 6 8 7 txout + out to phy txout C spare + rxout + rxout C 16 14 15 11 9 10 c19 47pf c13 470pf v out + v out C r24 100k r28 10k r23 3.65k 1% r13 30.1k 1% r17 10k r14 100k r11 10k r10 62k r25 62k r26 10k r27 62k c20 0.47 f c21 0.1 f notes: unless otherwise specified 1. all resistors are 5% 2. all capacitors are 25v 3. select r class for class 1-4 operation. refer to data sheet applications information section 4. connect to chassis ground c4 to c6: tdk c4532x5r0j107m c2, c23: avx 1808gc102mat d1, d7: mm3z12vt1 d3: mmbd1505 d9 to d12, d14 to d16: diodes inc., b1100 l1: coilcraft d01608c-472 t1: pulse h2019 t2: pulse pb2134 t3: pulse pa0184 oscap sfst t on endly minenab lt1737cgn r ocmp v cc r cmpc uvlo gate sgnd pgnd v c fb 3v out i sense c22 680pf 0603 d8 bat54 d5 b0540w c17 3300pf r15 0.22 ? 1/2w 1% r4 10k t2 separating line for ground plane t3 8 d7 12v 1 c12 0.1 f 50v c10 4.7 f 35v r16 330 ? c16 0.1 f 50v c23 1000pf 2kv ? 9 10 3 ? 5 4 c18 1nf r18 100 ? q6 si7892dp q7 fmmt718 q8 mmbt3904 8 11 c14 1 f r12 47 ? c4 to c6 100 f 6.3v 3.3v @ 3.3a q3 si4490dy r class 1% nc r class nc v in c1b 0.82 f 100v c1c 0.82 f 100v l1 4.7 h q2 mmbt3904 q4 mmbt2907alt1 q5 mmbt3904 r9 100 ? r8 47 ? r6 47 ? c9 100pf d2 bat54 q1 mmbta06 d4 bas21lt1 d1 12v d3a d3b r7 33 ? 1/4w c1a 10 f 100v r5 47k + q9 2n7002 d13 mmsd4148 c11 0.1 f 100v d6 smaj58a r30 75 ? c24 0.01 f 200v r31 75 ? c25 0.01 f 200v r1 75 ? c7 0.01 f 200v r2 75 ? c3 0.01 f 200v c2 1000pf 2kv 42571 ta02 d10 b1100 d12 b1100 d9 b1100 d11 b1100 d17 b1100 d16 b1100 d15 b1100 d14 b1100 3 4 4 ltc4257cdd-1 gnd sigdisa pwrgd v out figure 11. pd power interface with 3.3v, 3.3a high efficiency isolated power supply
ltc4257-1 19 42571fb u package descriptio information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. s8 package 8-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610) dd package 8-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1698) .016 C .050 (0.406 C 1.270) .010 C .020 (0.254 C 0.508) 45 0 C 8 typ .008 C .010 (0.203 C 0.254) so8 0303 .053 C .069 (1.346 C 1.752) .014 C .019 (0.355 C 0.483) typ .004 C .010 (0.101 C 0.254) .050 (1.270) bsc 1 2 3 4 .150 C .157 (3.810 C 3.988) note 3 8 7 6 5 .189 C .197 (4.801 C 5.004) note 3 .228 C .244 (5.791 C 6.197) .245 min .160 .005 recommended solder pad layout .045 .005 .050 bsc .030 .005 typ inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm) 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-1) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on top and bottom of package 0.38 0.10 bottom viewexposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ 2.38 0.10 (2 sides) 1 4 8 5 pin 1 top mark (note 6) 0.200 ref 0.00 C 0.05 (dd8) dfn 1203 0.25 0.05 2.38 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.50 bsc 0.675 0.05 3.5 0.05 package outline 0.25 0.05 0.50 bsc
ltc4257-1 20 42571fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2003 lt 1205 1k rev b ? printed in usa pd power interface with 3.3v, 3a nonisolated power supply typical applicatio u 1 3 2 rx C 6 rx + 3 tx C 2 tx + j1 t1 xfmr rj45 1 7 8 5 4 spare C spare + 6 8 7 txout + txout C rxout + rxout C to phy r12 75 ? r11 75 ? 75 ? c4 0.01 f 200v c3 0.01 f 200v 0.01 f 200v 0.01 f 200v c8 0.001 f 2kv 16 14 15 11 9 10 c14 0.1 f 100v ltc4257-1 ltc1871 q3 fdc2512 c1a 4.7 f 100v q2 fmmt625 d3 tvs smaj58a d4 mmbz5235b 6.8v r class 1% nc r class nc v in gnd sigdisa pwrgd v out run i th fb freq mode/sync sense v in intv cc gate gnd br2 df01sa ~+ ~C br1 df01sa ~+ ~C c1b 2.2 f 100v r10 100k r t 80.6k 1% r14 12.4k 1% r15 21k 1% c6 1 f 6.3v q1 2n7002 c c1 1nf r c 12k r17 750 ? r13 100k l1 1 h r16 100 ? q4 fmmt2222 d6 1n4148 r9 100k r18 10k + notes: unless otherwise specified 1. all resistor values are 5% 2. select r class for class 1-4 operation. refer to data sheet applications information section 3. connect to chassis ground c1a: panasonic ecev2aa4r7p c1b: tdk c5750x7r2a225kt c8: avx 1808gc102mat c9, c10, c12, c13: tdk c4532x5roj107 l1: lqlb2518t1rom t1: pulse h2019 r5 0.1 ? 1% c5 4.7 f 6.3v ? 4 2 11 9 t2 ctx-02-15242 d5 ups840 12 4257 ta03 10 ?? c9 100 f x5r 6.3v c10 100 f x5r 6.3v v out + 3.3v at 3a v out C + + c12 100 f x5r 6.3v c13 100 f x5r 6.3v + + 3 2 75 ? related parts part number description comments ltc1737 high power isolated flyback controller sense output voltage directly from primary-side winding ltc1871 wide input range, no r sense ? current mode flyback, adjustable switching frequency, programmable undervoltage boost and sepic controller lockout, optional burst mode ? operation at light load ltc3803 current mode flyback dc/dc controller in thinsot? 200khz constant frequency, adjustable slope compensation, optimized for high input voltage applications ltc4257 ieee 802.3af pd interface controller 100v, 400ma internal switch, programmable classification ltc4258 quad ieee 802.3af power over ethernet controller dc disconnect only, ieee-compliant pd detection and classification, autonomous operation or i 2 c? control ltc4259a-1 quad ieee 802.3af power over ethernet controller ac or dc disconnect, ieee-compliant pd detection and classification, autonomous operation or i 2 c control ltc4267 ieee 802.3af pd interface controller with onboard 100v, 400ma internal switch, 16-pin ssop or 3mm 5mm integrated switching regulator dfn packages burst mode is a registered trademark of linear technology corporation. no r sense and thinsot are trademarks of linear technology corporation.

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